Defect Diagnosis Group

English Publications

Abstracts

Harp Test Structure to Electrically Determine Size Distributions of Killer Defects Christopher Hess, Larg H. Weiland Abstract - To improve accuracy of electrically based measurements of defect densities and defect size distributions, we present a novel Harp Test Structure (HTS). There, horizontal and vertical parallel lines will be placed inside a given boundary pad frame without using any additional active semiconductor devices. The enhanced 2D-Permutation Sequence provides that all neighborhood relationships of adjacent test structure lines are unique. This is the key to disentangle even multiple faults detected by fast digital measurements. For this reason, the number and size of individual defects will be extracted anywhere inside or in-between layers. Experimental results show, that not only optical measurements, but also electrical measurements at a Harp Test Structure are sufficient to get a precise defect size distribution that enables size distribution modeling for yield prediction. IEEE Transactions on Semiconductor Manufacturing, pp. 194-203, Vol. 11, No. 2, 1998

Wafer Level Defect Density Distribution Using Checkerboard Test Structures Christopher Hess, Larg H. Weiland Abstract - Defect density distributions play an important role in process control and yield prediction. To improve the accuracy in modeling defect density distributions we present a wafer level methodology to analyze defect data measured anywhere on a wafer. So, the inspected area may be limited to test structures that just cover a fraction of each wafer. For that, imaginary wafermaps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations a Micro Density Distribution (MDD) will be determined for each wafer that reflects the degree of defect clustering. The single MDDs per wafer may be summarized to also provide a General Defect Density Distribution per lot or any other sample size. Proc. International Conference on Microelectronic Test Structures (ICMTS) ,pp. 101-106, Kanazawa (Japan), 1998 Full paper (111k Adobe Acrobat PDF 3.0 document)

Strategy to Disentangle Multiple Faults to Identify Random Defects within Test Structures Christopher Hess, Larg H. Weiland Abstract - Defect inspection is required for process control and to enhance chip yield. Electrical measurements at test structures are commonly used to detect faults. To improve the accuracy to evaluate the defects that have caused such faults, this paper presents a strategy to analyze single and multiple faults to precisely determine the number, layer and location of randomly distributed defects within a test structure layout. For that we first discuss the possibilities to analyze faults within known test structure layouts. Then, we present modified test structure layouts to improve the analysis of multiple faults. Finally we introduce a methodology to disentangle multiple faults by calculating and comparing the probability of possible defect locations within large test structure layout areas. Proc. International Conference on Microelectronic Test Structures (ICMTS) ,pp. 141-146, Kanazawa (Japan), 1998 Full paper (135k Adobe Acrobat PDF 3.0 document)

Novel Methodology to Include all Measured Extension Values per Defect to Improve Defect Size Distributions Christopher Hess, Larg H. Weiland Abstract - Defect size distributions play an important role in process characterization and yield prediction. To reduce time and costs of defect size extraction procedures the paper presents a novel methodology to determine defect size distributions. For that, we use all measured defect extension values per inspected defect compared to known methodologies just using one size value per defect. Our approach enables a reduction of the sample of defects to be inspected in semiconductor manufacturing fabs. Nevertheless, the novel methodology will provide even better accuracy of defect size distributions. Proc. Advanced Semiconductor Manufacturing Conference (ASMC), Boston (USA), 1998 Full paper (138k Adobe Acrobat PDF 3.0 document)

Determination of Defect Size Distributions Based on Electrical Measurements at a Novel Harp Test Structure Christopher Hess, Larg H. Weiland Abstract - To improve accuracy of electrically based measurements of defect densities and defect size distributions, we present a novel harp test structure. There, horizontal and vertical parallel lines will be placed inside a given boundary pad frame without using any additional active semiconductor devices. An enhanced permutation procedure provides that all neighborhood relationships of adjacent test structure lines are unique. This is the key to disentangle even multiple faults detected by fast digital measurements. For this reason, the number and size of individual defects will be extracted anywhere inside or in-between layers. Proc. International Conference on Microelectronic Test Structures (ICMTS) , pp. 1-6, Monterey (USA), 1997 Full paper (598k Adobe Acrobat PDF document)

Issues on Short Circuits in Large On-Chip Power MOS-Transistors Using a Modified Checkerboard Test Structure Christopher Hess, Larg H. Weiland, Ralf Bornefeld* Abstract - To control random quality deviation of large on-chip power MOS-transistors, we have developed a modified checkerboard test structure. Using this structure, the complete chip area is divided into distinguishable subchips, each containing one large area power MOS-transistor. The fast digital measurements and the precise localization of transistor short circuits guarantee a fast process classification and enable additional electrical and optical defect parameter extraction. Proc. International Conference on Microelectronic Test Structures (ICMTS) , pp. 146-150, Monterey (USA), 1997; * author is with ELMOS Elektronik in MOS-Technologie GmbH Dortmund, Germany Full paper (802k Adobe Acrobat PDF document)

Customized Checkerboard Test Structures to Localize Interconnection Point Defects Christopher Hess, Larg H. Weiland, Ralf Bornefeld* Abstract - To localize point defects that occur inside numerous interconnection layers, a multilevel Checkerboard Test Structure is presented. Here, the large defect sensitive area inside boundary pads is divided into many distinguishable subchips. To provide test structure data that reflect yield of product chips, each subchip layout will be customized to real circuit designs of product chips. Defects are detected and localized by simple electrical measurements. Only the layer specific defect localization enables precise defect parameter extraction to provide detailed defect statistics and process problem debugging. Proc. VLSI Multilevel Interconnection Conference (VMIC), pp. 163-168, Santa Clara (USA), 1997; * author is with ELMOS Elektronik in MOS-Technologie GmbH Dortmund, Germany Full paper (810k Adobe Acrobat PDF document)

Comparison of Defect Size Distributions Based on Electrical and Optical Measurement Procedures Christopher Hess, Larg H. Weiland Abstract - Defect size distributions play an important role in process characterization and yield prediction. To determine efficient procedures to extract defect size distributions, a data base was set up that consists of hundreds of defect images to provide defect size distributions also reflecting irregular outlines of defects. Further investigation results that even a single extension value per defect may provide a precise size distribution. Furthermore, the proposed Harp Test Structure (HTS) containing hundreds of parallel lines will also provide a defect size distribution, but it is based on electrical measurements only. The comparison of defect size distributions using both measurement procedures results that not only optical measurements, but also electrical measurements at a Harp Test Structure are sufficient to get a precise defect size distribution that also enables size distribution modeling for yield prediction. Proc. Advanced Semiconductor Manufacturing Conference (ASMC), pp. 277-282, Boston (USA), 1997 Full paper (247k Adobe Acrobat PDF 3.0 document)

Defect Cluster Analysis to Detect Equipment Specific Yield Loss Based on Yield-to-Area Calculations Christopher Hess, Larg H. Weiland Abstract - Defect parameter extraction plays an important role in process control and yield prediction. A methodology of evaluating wafer level defect clustering will be presented to detect equipment specific particle contamination. For that, imaginary wafermaps of a variety of different chip areas are generated to calculate a yield-to-area dependency. Based on these calculations a Micro Density Distribution (MDD) will be determined for each wafer. The range and course of the MDD may indicate specific failures of equipment tools. Proc. 1997 SPIE'sMicroelectronic Manufacturing: Yield, Reliability, and Failure Analysis, Spie Vol. 3216, pp. 126-137, Austin (USA), 1997 Full paper (366k Adobe Acrobat PDF 3.0 document)

Influence of Short Circuits on Data of Contact & Via Open Circuits Determined by a Novel Weave Test Structure Christopher Hess, Larg H. Weiland Abstract - Generally test structures containing via strings and contact strings are used to control backend isolation layers' integrity. But, short circuits are the major type of fault resulting from defects during the backend process steps. For that, the influence that short circuits have on contact hole open circuits and via hole open circuits in regular string test structures will be investigated here. A novel weave test structure (WTS) is presented to detect open circuits as well as short circuits in adjacent conducting layers of backend process steps. Numerous contact strings or via strings are arranged inside boundary pads like a woven piece of cloth. So, also short circuits between different strings are electrically detectable. The separation and localization of defects will be achieved by dividing the chip area into distinguishable subchips inside given standard boundary pads without using any active semiconductor devices. The localization enables a versatile optical defect parameter extraction to precisely determine the reason why and how a defect occurred during the manufacturing process. IEEE Transactions on Semiconductor Manufacturing, pp. 27-34, Vol. 9, No. 1, 1996

Control of Application Specific Interconnection on Gate Arrays Using an Active Checkerboard Test Structure Christopher Hess, Larg H. Weiland, Günter Lau*, Peter Simoneit* Abstract - To control interconnection layers' integrity on application specific gate arrays, a novel active checkerboard test structure (ACTS) is presented. Here, the total gate array area will be divided into distinguishable small subchips, each containing basic layout elements like different sized serpentine lines or via strings. The precise separation and localization of these test structure elements inside the subchips facilitate versatile classification of interconnection faults, additional defect parameter extraction, and defect statistics. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 55-60, Trento (Italy), 1996; * authors are with Thesys Gesellschaft für Mikroelektronik mbH Full paper (380k Adobe Acrobat PDF document)

Correlation between Particle Defects and Electrical Faults determined with Laser Scattering Systems and Digital Measurements on Checkerboard Test Structures Christopher Hess, Larg H. Weiland, Günter Lau*, Rainer Hiller* Abstract - To improve accuracy of defect densities, yield prediction and failure analysis, this paper compares data on defects and faults collected by electrical measurement methods and laser scattering systems. For that we choose the checkerboard test structure design to partition the whole chip area into a large number of subchips, each containing defect sensitive comb lines. A digital tester based measurement procedure enables the detection and separation of faults. Additional analysis procedures guarantee a layer-specific fault localization inside specific subchips. Manufacturing of test chips at Thesys Gesellschaft für Mikroelektronik was accompanied by laser scattering after selected processed layers. Finally, wafermaps based on electrically detected faults and optically detected particle defects were analyzed to determine correlations between defects and faults. Proc. 1996 SPIE's Microelectronic Manufacturing: Yield, Reliability, and Failure Analysis II, Spie Vol. 2874, pp. 64-74, Austin (USA), 1996; * authors are with Thesys Gesellschaft für Mikroelektronik mbH Full paper (312k Adobe Acrobat PDF 3.0 document)

Issues on the Size and Outline of Killer Defects and their Influence on Yield Modeling Christopher Hess, Larg H. Weiland Abstract - Yield prediction models and critical area calculations base on defects modeled as circular disks. But, the observation of real defects provides mostly irregular defect outlines. For this reason, we investigate the influence of real defect outlines on determining defect size distributions for yield prediction. To collect data on defects, checkerboard test structures were manufactured that enable a precise localization of defects inside large chip areas. Furthermore, we introduce a methodology to calculate a general defect size distribution that includes variety of real defect outlines. So, this realistic size distribution will be compared to defect size distributions based on known yield models to describe defect outlines. Proc. Advanced Semiconductor Manufacturing Conference (ASMC), pp. 423-428, Boston (USA), 1996 Full paper (470k Adobe Acrobat PDF document)

Influence of Short Circuits on Data of Contact & Via Open Circuits Determined by a Novel Weave Test Structure Christopher Hess, Larg H. Weiland Abstract - The influence that short circuits have on contact hole open circuits and via hole open circuits in regular string test structures will be investigated. To detect open circuits as well as short circuits in adjacent conducting layers of backend process steps, a novel weave test structure (WTS) is presented. Numerous contact strings or via strings are arranged inside boundary pads like a woven piece of cloth. So, also short circuits between different strings are electrically detectable. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 11-16, Nara (Japan), 1995 Full paper (254k Adobe Acrobat PDF document)

Defect Parameter Extraction in Backend Process Steps using a Multilayer Checkerboard Test Structure Christopher Hess, Larg H. Weiland Abstract - To control defect appearance in numerous conducting layers of backend process steps, a novel multilayer checkerboard test structure (MCTS) is presented. The Separation and localization of defects - causing electrically detectable intralayer short circuits as well as interlayer short circuits - will be achieved by dividing the chip area into distinguishable small subchips inside given standard boundary pads without using any active semiconductor devices. The precise localization facilitates a versatile optical defect parameter extraction. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 51-56, Nara (Japan), 1995 Full paper (797k Adobe Acrobat PDF document)

Resistance Modelling of Test Structures for Accurate Fault Detection in Backend Process Steps Using a Digital Tester Christopher Hess, Larg H. Weiland Abstract - A methodology is presented to enable the usage of a digital tester for an accurate detection of open circuits as well as short circuits in test structures to control backend process steps. Therefore, a novel graph model will be introduced to calculate the resistance values of test structures containing defects. The paper gives a comprehensive description of the procedure to adjust the tester parameters to those test structures. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 265-270, Nara (Japan), 1995 Full paper (325k Adobe Acrobat PDF document)

A Digital Tester Based Measurement Methodology for Process Control in Multilevel Metallization Systems Christopher Hess, Larg H. Weiland Abstract - The control of metallization layers' integrity gain more importance increasing the total number of metallization layers. Therefore, an electrical measurement procedure has to separate defectless test structure elements from faulty test structure elements. To decrease the number of test procedures and test equipment, this binary decision will be made parallel to the functional test of product chips using the same digital test system to measure test structure elements too. In addition, the geometrical arrangement of the test structure layout elements will also be transformed to a binary description. As a result of this, novel algorithms will now enable the direct comparison of both binary data sets to extract test structure faults like opens and shorts as well as process specific defect parameters. Proc. 1995 SPIE's Microelectronic Manufacturing: Process, Equipment, and Matrials Control in Integrated Circuit Manufacturing, Spie Vol. 2637, pp. 125-136, Austin (USA), 1995 Full paper (103k Adobe Acrobat PDF 3.0 document)

Modeling of Real Defect Outlines and Defect Parameter Extraction Using a Checkerboard Test Structure to Localize Defects Christopher Hess, Albrecht P. Stroele Abstract - For efficient yield prediction and inductive fault analysis, it is usually assumed that defects have the shape of circular discs or squares. Real defects, however, exhibit a great variety of different shapes. This paper presents a more accurate model. The defect outline is approximated by an ellipse, and an equivalent circular defect is determined that causes a fault with the same probability as the real defect. To utilize this model, only the maximum and the minimum extension of detected defects have to be determined. That can be done easily using a novel test structure design. The checkerboard test structure uses the boundary pad frame of standard chips and thus achieves a large defect sensitive area. This area is partitioned into many small regions that can be analyzed separately. Defects are localized by simple electrical measurements. This allows an efficient optical inspection that can provide detailed information about the detected defects. IEEE Transactions on Semiconductor Manufacturing, pp. 284-292, Vol. 7, No. 3, 1994

Modeling of Test Structures for Efficient Online Defect Monitoring Using a Digital Tester Christopher Hess, Larg H. Weiland Abstract - A novel methodology for digital measuring procedures and digital data analysis is presented in order to evaluate an online process control and defect monitoring. That can be done by manufacturing test chips side by side with standard chips and measuring them with the same measuring equipment - the digital tester. To achieve a fast and effective (efficient) measuring procedure and data analysis test structures will be modeled in geometry-graphs, neighborhood-graphs and connection-graphs. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 108-113, San Diego (USA), 1994 Full paper (644k Adobe Acrobat PDF document)

Drop in Process Control Checkerboard Test Structure for Efficient Online Process Characterization and Defect Problem Debugging Christopher Hess, Larg H. Weiland Abstract - A novel diode-checkerboard test structure (DCTS) is presented to determine open circuit defects and short circuit defects as well as to investigate the 3D-influence of underlying topography. The arrangement of the DCTS in a standard boundary pad frame and the digitally measuring procedure evaluate a fast and effective (efficient) online process characterization. The precise defect detection and localization facilitate an additional optical defect problem debugging. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 152-159, San Diego (USA), 1994 Full paper (612k Adobe Acrobat PDF document)

Strategy to Optimize the Development, Use, and Dimension of Test Structures to Control Defect Appearance in Backend Process Steps Christopher Hess Abstract - To inspect and classify defects occurring during backend process steps, this paper describes a comprehensive methodology how to develop, use, and dimension test structures and how to optimize their organization inside given test chip boundaries. Starting point is the description of process steps and known types of defects. According to existing design rules different test structures will be designed and arranged as (in- line) process monitors inside a checkerboard framework using standard boundary pads. Proc. Advanced Semiconductor Manufacturing Conference (ASMC), pp. 282-289, Boston (USA), 1994 Full paper (562k Adobe Acrobat PDF document)

Modeling of Real Defect Outlines for Defect Size Distribution and Yield Prediction Christopher Hess, Albrecht P. Stroele Abstract - For efficient yield prediction defects are usually modeled by circular discs or squares. This paper presents a more accurate model that considers the real outline of physical defects. To utilize this model only the maximum and the minimum extension of detected defects have to be determined. That can be done easily using a checkerboard test structure including a defect localization procedure. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 75-80, Barcelona (Spain), 1993 Full paper (774k Adobe Acrobat PDF document)

Test Structure for the Detection, Localization, and Identification of Short Circuits with a High Speed Digital Tester Christopher Hess, Larg H. Weiland Abstract - A test structure, which can detect short circuits in a 2-metal-layer process is placed in a test chip, which will be manufactured side by side with standard chips and will be measured with exactly the same electrical test equipment as standard chips (digital tester for boundary pads). The analysis of this data offer the detection and identification of random defects and also the possibility of fixing the position of these defects inside the test chip, which facilitates an additional optical measurement for determining the causes, sizes and outlines of the defects. Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 139-144, San Diego (USA), 1992

© 7/1998 C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, Karlsruhe