Publications

 

V. Sabelfeld and K. Kapp
Arithmetics in Formal Synthesis 
In:  R. Drechsler (Ed.) GI/ITG/GMM Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Shaker Verlag, Aachen 2003, pp. 112 - 120.


K. Kapp and V. Sabelfeld
Dead Code Elimination in Formal Synthesis 
In:  R. Drechsler (Ed.) GI/ITG/GMM Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Shaker Verlag, Aachen 2003 , pp. 121-130.


V. Sabelfeld, C. Blumenröhr and K. Kapp
Semantics and Transformations in Formal Synthesis at System Level
In:  Dines Bjorner, Manfred Broy, Alexandre Zamulin (Eds.) Perspectives of System Informatics, 4th International Andrei Ershov Memorial Conference , July 2-6, 2001, Novosibirsk, Russia, LNCS 2244, 2001, pp. 149-156, Springer-Verlag.
V. Sabelfeld  
"The tree equivalence of linear recursion schemes" 
Theoretical Computer Science, 2000
 
C. Blumenröhr 
"Formale Spezifikation und Synthese digitaler Schaltungen auf höheren Abstraktionsebenen"
Dissertation 

C. Blumenröhr, V. Sabelfeld 
"Formal Synthesis at the Algorithmic Level"
Charme'99 

D. Eisenbiegler 
"Ein Kalkül für die Formale Schaltungssynthese"
Dissertation

C. Blumenröhr 
"A Formal Approach to Specify and Synthesize at the System Level"
GI/ITG/GMM Verification Workshop'99 

D. Eisenbiegler, C. Blumenröhr 
"Reuse Concepts in Gropius"
Kluwer

C. Blumenröhr, D. Eisenbiegler, D. Schmid 
"On the Efficiency of Formal Synthesis -- Experimental Results"
TCAD

D. Eisenbiegler, C. Blumenröhr 
"Gropius - Advanced Reuse Concepts in a New Hardware Description Language"
GI/ITG/GMM Reuse Workshop'98

C. Blumenröhr, D. Eisenbiegler 
"Performing High-Level Synthesis via Program Transformations within a Theorem Prover"
Euromicro'98

C. Blumenröhr, D. Eisenbiegler 
"Deriving Structural RT-Implementations from Algorithmic Descriptions by means of Logical Transformations"
GI/ITG/GMM Verification Workshop'98

C. Blumenröhr, D. Eisenbiegler 
"An Efficient Representation for Formal Synthesis"
ISSS'97

D. Eisenbiegler 
"Automata - A Theory Dedicated towards Formal Circuit Synthesis"
Technischer Bericht, Fakultät für Informatik, Universität Karlsruhe

D. Eisenbiegler 
"Possibilities, Limitations and Problems in Retiming - a View from a Logical Perspective"
GI/ITG/GME Workshop '97

D. Eisenbiegler, R. Kumar, C. Blumenröhr 
"A Constructive Approach towards Correctness of Synthesis - Application within Retiming"
EDTC'97

C. Blumenröhr, D. Eisenbiegler, R. Kumar 
"Applicability of Formal Synthesis Illustrated via Scheduling" 
IWLAS'96

R. Kumar, C. Blumenröhr, D. Eisenbiegler and D. Schmid 
"Formal Synthesis in Circuit Design - A Classification and Survey" 
FMCAD'96

D. Eisenbiegler, C. Blumenröhr and R. Kumar 
"Implementation Issues about the Embedding of Existing High Level Synthesis Algorithms in HOL"
TPHOL'96

R. Kumar, D. Eisenbiegler 
"Synthese von Verhaltensbeschreibungen in VHDL mittels logischer Transformationen"
GI/ITG/GME'96

D. Eisenbiegler, R. Kumar, J. Müller 
"A Formal Model for a VHDL Subset of Synchronous Circuits"
APCHDL'96

D. Eisenbiegler, R. Kumar 
"ABC-VHDL, A Synchronous VHDL Subset with a Formal Semantics in HOL" 
FZI Report 8/95

D. Eisenbiegler, R. Kumar 
"Formally Embedding Existing High Level Synthesis Algorithms"
CHARME'95

D. Eisenbiegler, R. Kumar 
"An Automata Theory Dedicated towards Formal Circuit Synthesis" 
HUG'95

D. Eisenbiegler, R. Kumar 
"Evaluation Techniques as a Part of the Verification Process"
HUG'94

D. Eisenbiegler, K. Schneider, R. Kumar 
"Ein funktionaler Ansatz zur systematischen Formalisierung regulärer Schaltungen"
SFB358-C2-15/93

D. Eisenbiegler, K. Schneider, R. Kumar 
"A Functional Approach for Formalizing Regular Hardware Structures" 
HUG'93